In many multiprocessor systems, all of the processors access a common memory, referred to as the main memory. Typically, the main memory is not capable of supplying data and instructions to multiple processors at adequate speeds. To compensate for the speed deficiencies of main memory, caches are usually incorporated. Caches are small high-speed memories located between main memory and a processor, and that are updated to contain memory data that was recently requested by the processor. The processor can generally obtain a copy of memory data much more quickly from its cache than from the main memory.
In multiprocessor systems, multiple copies of a particular data item may reside within multiple caches at any given time. Because of this, a memory coherency protocol must be used to ensure that all processors within the system operate from the same, most recent, copy of the memory data. This type of protocol allows data to be shared among many devices for read-only purposes. Before a device can modify the data, it must gain exclusive access to the data. In this case, all other cached copies of the data are marked as unusable, or “invalidated”. After a device gains exclusive access to data, the device may, but is not required to, modify the data. When a device relinquishes exclusive access rights, any updated copy of the data must be stored back to the main memory, or provided to another cache within the system.
In a multiprocessor system of the type discussed above, gaining access to data may be time-consuming. First a requester such as an instruction processor or I/O module makes a request for the data from its associated caches. If a cache miss occurs, the request must be forwarded to the main memory. The main memory then determines whether it has the most recent copy of the requested data. In some cases, another cache in the system may store another, more recent copy of the data. The main memory therefore makes a request to this other cache to prompt return of any such copy. If the cache has such a copy, it may be forwarded to the requester. If, however, the cache does not have an updated copy, the main memory must again be accessed to obtain the data that will be returned to the requester. Thus, when a cache memory that may have an updated data copy is found to not store such a copy after all, two references to main memory are required to satisfy the request. This adds latency to the request path, and decreases overall system throughput.
What is needed, therefore, is an improved system and method for returning data to a requester in an accelerated manner.